The present invention relates to packaging integrated circuits, more particularly to the structure and processing of a stud and bump without the standard under bump metallurgy.
This invention involves the process and structure of forming an interconnect structure including a stud and a bump on an integrated circuit chip. Currently, in the semiconductor industry, an under bump metal (UBM) is applied on top of a base pad, where the base pad is typically aluminum or copper or their alloys. The UBM usually consists of a layer of chrome, a layer of chrome copper (CrCu), a layer of copper (Cu), and a layer of gold (Au) below an evaporative bump stud. For an electroplated bump, the UBM typically consists of a layer of titanium tungsten nitride (TiWNx), a layer of titanium tungsten (TiW) and a layer of copper below the stud. This under bump metallurgy is used as a solder diffusion barrier for obtaining good adhesion and for reducing stresses between the base pad and the stud.
The present invention provides an interconnect structure without the need for a UBM, thereby reducing process steps, manufacturing cost and increasing reliability. In the present invention, a stud is applied directly to the base pad using substantially the same base material. The advantages of this invention include the use of substantially the same base material for the stud and for the bond pad which decreases stress, reduces processing steps and cost, without creating an adhesion problem between the stud and base pad.